In order to improve efficiency of Very Large Scale Integration (VLSI) and reduce manufacturing cost, a gate pitch of a complementary metal oxide semiconductor (CMOS) transistor becomes smaller increasingly. However, reduction of the gate pitch causes short channel effects and lower performance of a device.
In Semiconductor On Insulator (SOI) technology, devices and circuits are formed on a semiconductor film on an insulating layer. Due to the existence of the insulating layer, complete dielectric isolation is realized between the devices and bulk silicon. Therefore, the latch-up effect in bulk silicon CMOS can be intrinsically avoided in an SOI-CMOS integrated circuit. In addition, the short channel effects of Fully Depleted SOI (FD-SOI) device are relatively small. A shallow junction is naturally formed and a leakage current is relatively small. Therefore, FD-SOI MOSFETs having an ultrathin body and double gates attract much attention. By providing a buried semiconductor layer under an ultrathin buried oxide layer (BOX) in an ultrathin SOI MOSFET and forming doped back gates for both an NFET and a PFET in the buried semiconductor layer, the threshold voltage can be adjusted effectively and the short channel effects can be suppressed. However, it is difficult to provide effective insulation between the devices and the back gates with such configuration. Consequently, it is difficult to control the back gate.
M. Khater et al. proposes a structure which combines STIs having double depths with double BOX substrates in “FDSOI CMOS with Dielectrically-Isolated Back gates and 30 nm Lg High-k/Metal Gate”, 2010 Symposium on VLSI Technology Digest of Technical Papers, 43-44. As shown in FIG. 1, there is a first buried layer 101 on a substrate 100 and a buried semiconductor layer on the first buried layer 101. The buried semiconductor layer is separated by a first STI 105 and forms a p+ doped back gate 102′ and an n+ doped back gate 102. There is a second buried layer 103 on the buried semiconductor layer, an SOI layer 104 on the second buried layer 103, and a gate stack on the SOI layer 104. The back gate 102 and the back gate 102′ are separated from the SOI layer 104 by a second isolation structure 106. Such configuration can effectively control the back gate of the NFET or the PFET, without increasing the leakage current. However, if such configuration is used, erosion of the STI structure in the semiconductor manufacture process possibly occurs such that the STI structure is eroded to the level where the buried semiconductor is located when contact plugs are formed, which may cause shorts between source/drain contacts and the buried semiconductor layer.